1. Technical Field
The present disclosure relates to high-speed latches and to high-speed dividers.
2. Background Information
A type of passive mixer in a downconverter of a radio receiver, or in an upconverter of a radio transmitter, is to be driven by 25% duty cycle signals I, IB, Q and QB. The I and Q signals differ from each other by 90 degrees. Signal IB is 180 degrees out of phase with respect to signal I. Signal QB is 180 degrees out of phase with respect to signal Q. The four 25% duty cycle signals are typically generated using a Phase-Locked Loop (PLL), where the PLL outputs a differential signal that in turn is divided down in frequency by two by a divide-by-two divider. The divide-by-two divider outputs the four 25% duty cycle signals I, IB, Q and QB that are supplied to drive the mixer. Such a divide-by-two divider can be made using two latches.
FIG. 1 (Prior Art) is a diagram of one type of latch. The latch is a dynamic latch that has nine transistors. The state of the latch is stored on the capacitance of a node within the circuit. The latch of FIG. 1, however, outputs a 50% duty cycle signal on the node QB. For addition information on the latch of FIG. 1, see: J. Yuan and C. Svensson, “A True Single-Phase-Clock Dynamic CMOS Circuit Technique”, IEEE J. Solid-State Circuits, vol. SC-22, no. 5, pages 899-901 (October 1987).
FIG. 2 (Prior Art) is a diagram of another type of dynamic latch. The latch is illustrated with its QB output coupled back to its D input to make a toggling circuit. Unfortunately, the toggling circuit of FIG. 2 outputs a 50% duty cycle signal. For addition information on the latch of FIG. 2, see: Q. Huang and R. Rogenmoser, “Speed Optimization Of Edge-Triggered CMOS For GHz Single-Phase Clock”, IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pages 456-464 (March 1996).
FIG. 3 (Prior Art) is a diagram of a prior art divider that does output 25% duty cycle signals. The divider is sometimes referred to as a pseudo-CML divider. Incoming clock signals are received into the Gm block shown at the top of the diagram. The circuit then outputs 25% duty cycle output signals I, IB, Q and QB, where the output signals are taken from the nodes between the P-channel and N-channel transistors. Although the circuit of FIG. 3 outputs the desired 25% duty cycle signals, the circuit consumes a lot of current. An improved divider circuit is sought that outputs 25% duty cycle signals suitable to drive the passive mixer, but that consumes a smaller amount of current than the circuit of FIG. 3.